September 27, 2021
| Start Time | End Time | Rooms | Session |
| 8:00AM | 9:00AM | Breakfast | |
| 8:30AM | 9:30AM | Monet | Plenary I: “TCAD simulation of advanced logic technologies” |
| 9:50AM | 11:40AM | Monet | S01: Advanced scaling & SRAM |
| 10:00AM | 11:40AM | Morocco | S02: Power electronics |
| 11:45AM | 12:45PM | Lunch | |
| 1:15PM | 4:00PM | Monet | S03: Novel simulation methodologies |
| 1:15PM | 4:00PM | Morocco | S04: Steep slope devices |
| 4:15PM | 6:00PM | Monet | On-site paper & late news discussion |
| 6:00PM | 7:00PM | Monet | Reception |
| 8:00PM | 9:00PM | Monet | Plenary II: Evening Plenary “Challenges in Design and Modeling of Cold CMOS HPC Technology” |
September 28, 2021
| Start Time | End Time | Rooms | Session |
| 7:30AM | 8:30AM | Virtual paper discussion | |
| 8:00AM | 9:00AM | Breakfast | |
| 8:30AM | 9:30AM | Monet | Plenary III: “Memory Technology 2021: Trends & Challenges” |
| 9:35AM | 12 Noon | Monet | S05: First principles |
| 9:45AM | 12 Noon | Morocco | S06: Magnetism |
| 12 Noon | 1:00PM | Lunch | |
| 1:30PM | 4:15PM | Monet | S07: Two-dimensional Materials |
| 1:40PM | 3:00PM | Morocco | S08: Variability |
| 3:15PM | 3:55PM | Morocco | S09: Quantum transport |
| 4:15PM | 6:00PM | Monet | On-site paper & late news discussion |
| 7:00PM | 9:00PM | Monet | Media Grill and Bar |
September 29, 2021
| Start Time | End Time | Rooms | Session |
| 7:30AM | 8:30AM | Virtual paper discussion | |
| 8:00AM | 9:00AM | Breakfast | |
| 8:30AM | 9:30AM | Monet | Plenary IV: “Cost Simulations to Enable PPAC Aware Technology Development” |
| 9:45AM | 12 Noon | Monet | S10: Process simulation |
| 9:35AM | 12 Noon | Morocco | S11: Cryogenic simulation and parasitics |
| 12 Noon | 1:00PM | Lunch | |
| 1:20PM | 3:00PM | Monet | S12: Circuit simulation & Compact models |
| 1:30PM | 3:00PM | Monet | S13: Optoelectronics |
September 30, 2021
| Start Time | End Time | Rooms | Session |
| 7:30AM | 8:30AM | Virtual paper discussion |
Plenary I
| “TCAD for logic technology process development”
Stephen Cea, Senior Principal Engineer, Intel Corporation |
S01: Advanced scaling & SRAM
Chair : Oskar Baumgartner (Global TCAD Solutions)| S1.1 (9:50AM): Invited:TCAD challenges and opportunities to find a feasible device architecture for sub-3nm scaling
Uihui Kwon, Yonghee Park, Yoon-Suk Kim, Jaehyun Yoo, and Dae Sin Kim (Samsung Electronics Corp. Ltd., Korea) |
| S1.2 (10:20AM): Complementary FET for Advanced Technology Nodes: Where Does It Stand? Liu Jiang, Ashish Pal, El Mehdi Bazizi, He Ren, Mehul Naik, Blessy Alexander and Buvna Ayyagari-Sangamalli (Applied Materials Inc., Santa Clara, California, USA) |
| S1.3 (10:40AM) : Variability-Aware DTCO Flow: Projections to N3 FinFET and Nanosheet 6T SRAM M. Karner, G. Rzepa, O. Baumgartner, G. Strof, F. Schanovsky, F. Mitterbauer, C. Kernstock, H.W. Karner, and Z. Stanojevi (Global TCAD Solutions, Vienna, Austria) |
|
S1.4 (11:00AM): Nanosheet Width Investigation for Gate-All-Around Devices Targeting SRAM Application Ashish Pal, El Mehdi Bazizi, Benjamin Colombeau, Blessy Alexander, and Buvna Ayyagari-Sangamalli (Applied Materials, Santa Clara, USA) |
| S1.5 (11.20AM): Combined Process Simulation and Emulation of an SRAM Cell of the 5nm Technology Node Xaver Klemenschits, Siegfried Selberherr, and Lado Filipovic (Institute for Microelectronics, Wien, Austria) |
S02: Power Electronics
Chair: Devin Verreck (imec, Belgium)| S2.1 (10:00AM): Full band Monte Carlo analysis of the uniaxial stress impact on 4H-SiC high energy transport T.Nishimura, K. Eikyu, K. Sonoda, and T. Ogata (Renesas Electronics Corporation, Ibaraki, Japan) |
| S2.2 (10:20AM): 2D-TCAD Simulation Study of Capture Layer and Repellent Layer of Current Filament in Trench-Gate IGBTs
Takeshi Suwa (Toshiba Electronic Devices & Storage Corporation, Kawasaki, Japan) |
| S2.3 (10:40AM): Efficient TCAD Large-Signal temperature-dependent variability analysis of a FinFET power amplifier
E. Catoggio, S. Donati Guerrieri, F. Bonani, and G. Ghione (Dipartimento di Elettronica e Telecomunicazioni, Politecnico di Torino Corso Duca degli Abruzzi, Torino, Italy) |
| S2.4 (11:00AM): Temperature-dependent mobility modeling of GaN HEMTs by cellular automaton method
Koichi Fukuda1, Junichi Hattori1, Hidehiro Asai1, Junya Yaita2, and Junji Kotani2 (1AIST, Tsukuba, Japan and 2 Fujitsu Limited, Atsugi, Japan) |
| S2.5 (11:20AM): Miller-Capacitance Analysis of High-Voltage-MOSFETs and Optimization Strategies for Low-Power Dissipation
Takahiro Iizuka1, Mitiko Miura-Mattausch1, Dondee Serveza Navarro1, Hideyuki Kikuchihara1, Takuya Umeda1, Hans Jürgen Mattausch1, and Takao Yamamoto2 (1HiSIM Research Center, Hiroshima University, Higashi-Hiroshima, Japan and 2 Semiconductor Division, DENSO CORPORATION, Kariya, Japan) |
S03: Novel simulation methodologies
Chair: Victor Moroz (Synopsys, USA)| S3.1 (1:15PM):Invited: Advances of atomistic modeling in predictive TCAD applications
Jeff Wu1, and Blanka Magyari-Köpe2 (1Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan and 2TSMC, USA) |
| S3.2 (1:45PM): Acceleration of three-dimensional device simulation with the 3D convolutional neural network
Seung-Cheol Han, Jonghyun Choi, and Sung-Min Hong, (School of EECS, Gwangju Institute of Science and Technology, Gwangju, Republic of Korea) |
| S3.3 (2:05PM): Neural network model for implementation of electron-phonon scattering in nanoscale device simulations based on NEGF method
Department of Electrical and Electronic Engineering, Kobe University, Japan Souma, Satofumi; Ogawa, Matsuto |
| S3.4 (2:40PM): Using Long Short-Term Memory (LSTM) Network to Predict Negative-Bias Temperature Instability
Fanus Arefaine1, Meng Duan2, Ravi Tiwari3, Aadit Kapoor1, Lee Smith4, Souvik Mahapatra3, and Hiu Yung Wong5 (1Dept. of Computer Engineering, San Jose State University, San Jose, USA, 2Synopsys Northern Europe, Ltd., Glasgow, United Kingdom, 3Dept. of Electrical Engineering, Indian Institute of Tech., Bombay, Mumbai, India, 4Synopsys, Inc., Mountain View, USA and 5Dept. of Electrical Engineering, San Jose State University, San Jose, USA) |
| S3.5 (3:00PM): An Effective Simulation Methodology of Quantum Nanostructure based on Model Order Reduction
Martin Veresko and Ming-Cheng Cheng (Department of Electrical and Computer Engineering, Clarkson University, NY, USA) |
| S3.6 (3:20PM): Study of using Quantum Computer to Solve Poisson Equation in Gate Insulators
Hector Jose Morrel, and Hiu Yung Wong (Electrical Engineering, San Jose State University, San Jose, USA) |
| S3.7 (3:40PM): Multi-Element Thermal Modeling of Interconnects derived from a Projection-based Leaning Algorithm
Ming-Cheng Cheng, and Wangkun Jia (Dept. of Electrical and Computer Engineering, Clarkson University, NY, USA) |
S04: Steep slope devices
Chair: Sabyasachi Tiwari (The University of Texas at Dallas, USA)| S4.1 (1:15PM):Invited:Multi-Domain Ferroelectric FETs with Negative and Enhanced Positive Capacitance for Logic Applications
Atanu K. Saha and Sumeet K. Gupta (School of Electrical and Computer Engineering, Purdue University, USA) |
| S4.2 (1:45PM): Negative-Capacitance FETs for Advanced Nodes: Circuit Performance and Variability Analysis with Ferroelectric Dynamic Switching
Yen-Kai Lin1, Jing Wang1, Takeshi Okagaki2, Seonghoon Jin1, Anh-Tuan Pham1, Yonghee Park2, Uihui Kwon2, Woosung Choi1, and Dae Sin Kim2 (1Device Lab, Samsung Semiconductor, Inc., San Jose, CA, USA and 2Data & Information Technology Center, Samsung Electronics, South Korea) |
| S4.3 (2:05PM): On the Resiliency of NC-FinFET SRAMs against Variation: MFIS Structure
Aniket Gupta1, Nitanshu Chauhan1,2, Om Prakash3, and Hussam Amrouch4 (1Dept. of Electronics Engineering, National Institute of Technology (NIT), Uttarakhand, 2Dept. of Electronics and Communication Engineering, Indian Institute of Technology (IIT) Roorkee, India, 3Dept. of Computer Science, Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany, and 4Chair of Semiconductor Test and Reliability (STAR), University of Stuttgart, Germany) |
| S4.4 (2:40PM): Quantum transport simulations of short channel effects induced by domain interactions in ferroelectric FETs
Hyeongu Lee, and Mincheol Shin (School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Republic of Korea) |
| S4.5 (3:00PM): Electron-phonon scattering in cold-metal contacted two-dimensional semiconductor devices
Rutger Duflou1,2, Michel Houssa1, and Aryan Afzalian2 (1Dept. of Physics and Astronomy, KU Leuven, Leuven, Belgium and 2IMEC, Leuven, Belgium) |
| S4.6 (3:20PM): A Sub-kBT/q Dirac-source Graphene Nanoribbon Field-effect Transistor
E. Chen1, A. Sanchez-Soares2, T. Kelly2, G. Fagas2, and J. C. Greer3 (1Corporate Research, TSMC, Hsinchu, Taiwan, 2EOLAS Designs, Cork, Ireland and 3University of Nottingham Ningbo China, Ningbo, China) |
| S4.7 (3:40PM): Modeling and Assessment of Atomic Precision Advanced Manufacturing (APAM) Enabled Vertical Tunneling Field Effect Transistor
Xujiao Gaoa, Juan P. Mendez, Tzu-Ming Lu, Evan M. Anderson, DeAnna M. Campbell, Jeffrey A. Ivie, Scott W. Schmucker, Albert Grine, Ping Lu, Lisa A. Tracy, Reza Arghavani, and Shashank Misrab (Sandia National Laboratories, Albuquerque, NM, USA |
Plenary II
| Plenary Talk: Challenges in Design and Modeling of Cold CMOS HPC Technology
Victor Moroz, Jamil Kawa, Xi-Wei Lin, Andrew R. Brown, Plamen Asenov, Jaehyun Lee, Mohit Bajaj, Tyler Michalak, Craig Riddet, Alexei Svizhenko, Renato Hentschke, and SørenSmidstru (Synopsys, Mountain View, California, USA; Glasgow, UK; Bangalore, India;Hillsboro, Oregon; and Copenhagen, Denmark) |
Plennary III
| Plenary Talk: Memory Technology 2021: Trends & Challenges
Jeongdong Choe (TechInsights, Canada) |
S05: First principles
Chair: Leonard (Frank) Register (The University of Texas at Austin, USA)| S5.1 (9:35AM):Invited:First-principles investigation of amorphous n-type In2O3 for BEOL transistor
Yaoqiao Hu1, Wriddhi Chakraborty2, Huacheng Ye2, Suman Datta2, Kyeongjae Cho1(1University of Texas at Dallas, USA and 2University of Notre Dame, USA ) |
| S5.2 (10:05AM): First-principle Extraction of Surface Roughness in Si/Oxide Interfaces
Kantawong Vuttivorakulchai1, Mohammad Ali Pourghaderi1, Uihui Kwon, Márton Vörös2, Byounghak Lee2, Seonghoon Jin2, Yonghee Park1, Woosung Choi2, and Dae Sin Kim1 (1DIT Center, Samsung Electronics, Hwasung-si, Gyeonggi-do, South Korea and 2Device Laboratory, Samsung Semiconductor Inc., San Jose, California, USA) |
| S5.3 (10:25AM): Ab initio LCAO hybrid functional approach for accurate, large-scale electronic structure calculations of semiconductor materials, interfaces and gate stacks
Petr A. Khomyakov, Jess Wellendorff, Mattias Palsgaard, Tue Gunst, Haruhide Miyagi, Brecht Verstichel, Fabiano Corsetti, Vaida Arcisauskaite, Umberto Martinez, Anders Blom, and SørenSmidstru (Synopsys Quantum ATK, Copenhagen, Denmark) |
| S5.4 (11:00AM): Clusters of Defects as a Possible Origin of Random Telegraph Signal in Imager Devices: a DFT based Study
A. Jay1, D. Rideau2, V. Goiffon3, F. Cristiano1, P.L. Julliard2, A. Le Roch3, N. Richard4, S. De Gironcoli5, L. Martin-Samos5, and A. Hémeryck1 (1LAAS CNRS, Université de Toulouse, Toulouse, France, 2ST Microelectronics, Crolles, France, 3ISAE-SUPAERO, Université de Toulouse, Toulouse, France, 4CEA, DAM, DIF, Bruyères-le-Châtel, Arpajon, France, 5CNR-IOM, Democritos National Simulation Center, c/o SISSA, Trieste, Italy) |
| S5.5 (11:20AM): Investigating the use of HSE Hybrid Functionals to Improve Electron Transport Calculations in Si, Ge, Diamond, and SiC
Dallin Nielsen, Maarten Van de Put, and Massimo Fischetti (Dept. of Materials Science and Engineering, The University of Texas at Dallas) |
| S5.6 (11:40AM): A Comprehensive Modeling Approach of Electronic Properties in III-V Digital Alloys
Sheikh Z. Ahmed1, Jiyuan Zheng2, Yaohua Tan3, Joe C. Campbell1, and Avik W. Ghosh1,4 (1Dept. of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA, 2Beijing National Research Center for Information Science and Technology, Tsinghua University, Beijing, China, 3Synopsys Inc, Mountain View, CA, USA, 4Dept. of Physics, University of Virginia, Charlottesville, VA, USA) |
S06: Magnetism
Chair: Sumeet Gupta (Purdue University, USA)| S6.1 (9:45AM): Late News: Modal Stability of Spin-Hall Nano-Oscillators in Realistic Micromagnetic Simulations and Measurements
Corrado Carlo Maria Capriata, and Bengt Gunnar Malm (Division of Electronics and Embedded Systems, KTH – Royal Institute of Technology, Sweden) |
| S6.2 (10:05AM): Ab initio modeling of few-layer dilute magnetic semiconductors
Sabyasachi Tiwari1, 2, 3, Maarten Van de Put1, Bart Soree3, 4, 5, and William G. Vandenberghe1 (1Department of Materials Science and Engineering, UT Dallas, Texas, USA, 2Department of Materials Engineering, KU Leuven, Leuven, Belgium, 3imec, Belgium, Leuven, Belgium, 4Department of Electrical Engineering, KU Leuven, Leuven, Belgium, and 5Department of Physics, Universiteit Antwerpen, Antwerp, Belgium) |
| S6.3 (10:25AM): Electrical Transport and Thermoelectric Properties of Cr-doped Monolayer MoS2 and WS2 via Density Functional Theory and Boltzmann Transport Simulation
Chieh-Yang Chen1,2, and Yiming Li1,2,3,4 (1Parallel and Scientific Computing Laboratory, 2Institute of Communications Engineering, 3Institute of Biomedical Engineering, 4Department of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan) |
| S6.4 (11:00AM): Reinforcement Learning Approach for Sub-Critical Current SOT-MRAM Switching materials, interfaces and gate stacks
Johannes Ender1,2, Roberto L. de Orio2, Simone Fiorentini1, Siegfried Selberherr2, Wolfgang Goes3, and Viktor Sverdlov1,2 (1Christian Doppler Laboratory for Nonvolatile Magnetoresistive Memory and Logic at the 2Institute for Microelectronics, TU Wien, Wien, Austria, and 3Silvaco Europe Ltd., Cambridge, United Kingdom) |
| S6.5 (11:20AM): Spin and Charge Drift-Diffusion Approach to Torque Computation in Magnetic Tunnel Junctions
Simone Fiorentini1, Johannes Ender1,2, Roberto L. de Orio2, Siegfried Selberherr2, Wolfgang Goes3, and Viktor Sverdlov1,2 (1Christian Doppler Laboratory for Nonvolatile Magnetoresistive Memory and Logic at the 2Institute for Microelectronics, TU Wien, Wien, Austria, and 3Silvaco Europe Ltd., Cambridge, United Kingdom) |
| S6.6 (11:40AM): Critical Current Reduction of Field-Free Perpendicular SOT-MTJ by STT Assist Using Micromagnetic Simulation
Wei-Jen Chen1, Ya-Jui Tsou1, Huan-Chi Shih1, Pang-Chun Liu2, and C. W. Liu1,2 (1Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan and 2Graduate Institute of Photonics and Optoelectronics, National Taiwan University, Taipei, Taiwan) |
S07: Two-dimensional Materials
Chair: Yaoqiao Hu (The University of Texas at Dallas, USA)| S7.1 (1:30PM): Invited: Materials and Device Strategies for Nanoelectronic 3D Heterogeneous Integration
Guanyu Zhou, Tian Sun, Rehan Youna, Christopher L. Hinkle (Department of Electrical Engineering, University of Notre Dame, USA) |
| S7.2 (2:00PM): Ab-intio based electron-phonon scattering for 2D materials within the NEGF framework
Gautam Gaddemane1,2, Rutger Duflou1,2, Kiroubanand Sankaran1, Geoffrey Pourtois1, Michel Houssa1,2, and Aryan Afzalian1 (1imec, Leuven, Belgium and 2KU Leuven, Laboratory of Semiconductor Physics, Leuven, Belgium) |
| S7.3 (2:20PM): Theoretical study on strain-controllable gradient Schottky barrier of dumbbell-shape graphene nanoribbon-base for highly sensitive strain sensors
Qinqiang Zhang, Ken Suzuki, and Hideo Miura (Fracture and Reliability Research Institute, Tohoku University, Japan) |
| S7.4 (2:40PM): Modeling Contact Resistivity in Monolayer Molybdenum disulfide Edge contacts
Madhuchhanda Brahma1, Maarten L. Van de Put1, Edward Chen2, Massimo V. Fischetti1, and William G. Vandenberghe1 (Department of Materials Science and Engineering, The University of Texas at Dallas, and 2Corporate Research, TSMC, Hsinchu, Taiwan) |
| S7.5 (3:15PM): Bandstructure effects in phosphorene nanoribbon MOSFETs from NEGF simulations using a new DFT-based tight-binding Hamiltonian model
Mirko Poljak, and Mislav Matić (Computational Nanoelectronics Group, University of Zagreb, Faculty of Electrical Engineering and Computing, Croatia) |
| S7.6 (3:35PM): Late News: Coupled electro-thermal simulation of 2DFETs
Electrical and Computer Engineering Department, University of Massachusetts Amherst C. Foss, A. K. Majee, and Z. Aksamija |
| S7.7 (3:55PM): Ballistic quantum transport study of Al contacting silicane using empirical pseudopotentials
Peter Reyntjens, Maarten L. Van de Put, and William G. Vandenberghe (Department of Materials Science and Engineering, The University of Texas at Dallas, Texas, USA) |
S08: Variability
Chair: Blanka Magyari-Köpe (TSMC, USA)| S8.1 (1:40PM): Simulation-based DRAM Design Technology Co-Optimization: Why Random Dopant Fluctuations Matter
Salvatore Maria Amoroso1, Plamen Asenov1, Jaehyun Lee1, Andrew R. Brown1, Xi-Wei Lin2, Victor Moroz2 and Ethan Kao3 (1Synopsys Northern Europe Ltd., Glasgow, Scotland, UK, 2Synopsys Inc, Mountain View, CA, USA and 3Synopsys Taiwan Ltd., Hsinchu, Taiwan) |
| S8.2 (2:00PM): Statistical Device Modeling with Arbitrary Model-Parameter Distribution via Markov Chain Monte Carlo
Hiroki Tsukamoto, Song Bian and Takashi Sato (Graduate School of Informatics, Kyoto University, Japan) |
| S8.3 (2:20PM): Analysis of Thermal Concentration Failure in Unclamped Inductive Switching based on Three-dimensional Electro-Thermal Simulation with on-chip variation
Kyohei Shimozato, Yohei Nakamura and Takashi Sato (Graduate School of Informatics, Kyoto University, Japan) |
| S8.4 (2:40PM): Impact of metal grain granularity on three gate-all-around advanced architectures
J. G. Fernandez1, N. Seoane1, E. Comesaña1, K. Kalna2 and A. García-Loureiro1 (1CiTIUS, University of Santiago de Compostela, Spain and 2Nanoelectronic Devices Computational Group, Swansea University, U. K) |
S09: Quantum transport
Chair: Seonghoon Jin (Samsung, USA)| S9.1 (3:15PM): A Non-Equilibrium Green’s Function Approach to Majorana Bound States in nanowire Kitaev chains
Hamed Vakili1, Samiran Ganguly2, Bhaskaran Muralidharan2, and Avik W. Ghosh3 (1Dept. of Physics, University of Virginia, Charlottesville, VA, USA, 2Charles L. Brown Dept. of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA, and 3Dept. of Electrical Engineering, IIT Bombay, Mumbai, India) |
| S9.2 (3:35PM): Quantum Transport Simulations for Si: P δ-layer Tunnel Junctions
Juan P. Mendez, Denis Mamaluy, Xujiao Gao, and Shashank Misra (1Cognitive & Emerging Computing, 2Electrical Models & Simulation and 3Multiscale Fab. Sci. & Tech. Dev. Sandia National Laboratories, Albuquerque, NM, USA) |
Plenary IV
| Plenary Talk: Cost Simulations to Enable PPAC Aware Technology Development
Scotten W. Jones (IC Knowledge LLC, USA) |
S10: Process simulation
Chair: El Mehdi Bazizi (Applied Materials, USA)| S10.1 (9:45AM): Kinetic Monte Carlo for Process Simulation: First Principles Calibrated Parameters for BO2 Complex
P.L. Julliard1,2, A. Jay2, M. Gunde2,3, N. Salles3, F. Monsieur1, T. Cabout1, N. Guitard1, S. Joblot1, L. Martin-Samos3, D. Rideau1, F. Cristiano2 and A. Hémeryck2 (1STMicroelectronics, Crolles, France, 2LAAS-CNRS, Université de Toulouse, CNRS, Toulouse, France, and 3CNR-IOM, Trieste, Italy) |
| S10.2 (10:05AM): Fast Model for Deposition in Trenches using Geometric Advection
Lado Filipovic, and Xaver Klemenschits, (Institute for Microelectronics, TU Wien, Wien, Austria) |
| S10.3 (10:40AM): Surface Reaction and Topography Modeling of Fluorocarbon Plasma Etching
Frâncio Rodrigues1, Luiz Felipe Aguinsky1, Alexander Toifl1, Alexander Scharinger∗, Andreas Hössinger2, and Josef Weinbub1 (1Christian Doppler Laboratory for High Performance TCAD, Institute for Microelectronics, TU Wien, Wien, Austria, 2Silvaco Europe Ltd., Cambridge, United Kingdom) |
| S10.4 (11:00AM): Mechanism investigation of temperature dependent growth and etching process of GeCl4 on SiGe surface: ab initio study
Data & Information Technology Center, Samsung Electronics, 1-1, Samsungjeonja-ro, Hwaseong-si, Gyeonggi-do, South Korea Ji Young Park1, Gyeom Kim2, Jin Bum Kim2, Sang-Moon Lee2, Sae-jin Kim1, Hyoungsoo Ko1, Seungmin Lee1, Seung Hun Lee2, Inkook Jang1, and Dae Sin Kim1 (1CSE Team, Data & Information Technology Center, Samsung Electronics Co., Ltd., Korea, and 2Foundry Process Development Team, Semiconductor R&D Center, Smaung Electronics Co., Ltd., Korea) |
| S10.5 (11:20AM): Reactive Force-Field Molecular Dynamics Study of the Effect of Gaseous Species on Silicon-Germanium Alloy Growth by PECVD Techniques
Naoya Uene1, Takuya Mabuchi2, Masaru Zaitsu3, Shigeo Yasuhara3, and Takashi Tokumasi4 (1Graduate School of Engineering, Tohoku University, Japan, 2Frontier research institute for interdisciplinary sciences, Tohoku University, Japan, 3Rsearch & development, Japan advanced chemicals ltd., Japan and 4Institute of fluid science, Tohoku University, Japan) |
| S10.6 (11:40AM): TCAD Comprehensive Silicon Strain Model Using Finite Element Quasi-Fermi Discretization
Thomas Weingartner1, Mark E. Law1, Keith Green2, Andrew Thomas1, Henry Johnson1, and Polina Leger1 (1The Department of Electrical and Computer Engineering at the University of Florida, Gainesville, USA and 2Analog Technology Development, Texas Instruments, Dallas, USA) |
S11: Cryogenic simulation and parasitics
Chair: Stephen Cea (Intel, USA)| S11.1 (9:35AM): Invited: Transistor modelling for mm-Wave technology pathfinding
Bertrand Parvais1, R. ElKashlan1, H. Yu, A. Sibaja-Hernandez, B. Vermeersch, V. Putcha, P. Cardinael2, R. Rodriguez, A. Khaled, A. Alian, U. Peralagu, M. Zhao, S.Yadav, G.Gramegna, J. Van Driessche, N. Collaert (imec, Belgium, also with 1Vrije, Universiteit Brussels, Belgium and with 2UCLouvain, Louvain-la-Neuve, Belgium) |
| S11.2 (10:05AM): Considerations for DD Simulation at Cryogenic Temperature
Seonghoon Jin1, Anh-Tuan Pham1, Woosung Choi1, Mohammad Ali Pourghaderi2, Uihui Kwon2, and Dae Sin Kim2 (1Device Lab, AHQ(DS) R&D, Samsung Semiconductor Inc., San Jose, CA, USA and 2CSE Team, Data & Information Technology Center, Samsung Electronics, Korea) |
| S11.3 (10:40AM): TCAD Modeling of Cryogenic nMOSFET ON-State Current and Subthreshold Slope
Prabjot Dhillon1, Nguyen Cong Dao2, Philip H. W. Leong2, and Hiu Yung Wong1 (1Electrical Engineering, San Jose State University, USA and 2Electrical and Info. Engineering, The University of Sydney, Sydney, Australia) |
| S11.4 (11:00AM): Bridge-Defect Prediction in SRAM Circuits Using Random Forest, XGBoost, and LightGBM Learners
Joydeep Ghosh, Shang Yi Lim, and Aaron Voon-Yew Thean (Electrical & Computer Engineering, National University of Singapore, Singapore) |
| S11.5 (11:20AM): RFSOI n-MOSFET OI-Layer Ground-Plane Engineering with Quasi-3D Simulations
Daniel Connelly1, Hiu Yung Wong2, Richard Burton1, Hideki Takeuchi1, and Robert Mears1 (1Atomera, Inc and 2San Jose State University) |
| S11.6 (11:40AM): Program charge interference and mitigation in vertically scaled single and multiple-channel 3D NAND flash memory
D. Verreck, A. Arreghini, G. Van den bosch, A. Furn ́emont, and M. Rosmeulen (imec, Leuven, Belgium) |
S12: Circuit simulation & compact models
Chair: Markus Karner (Global TCAD Solutions, Austria)| S12.1 (1:20PM): Unified SPICE Model for any Transient Ionizing Radiation Response of SOI MOSFET
Neil Rostand, and Damien Lambert (CEA, DAM, DIF, Arpajon, France) |
| S12.2 (1:40PM): Compact SPICE Model of Topological Textures on Magnetic Racetracks for Design Space Exploration
Sakib, Mohammad Nazmus; Vakili, Hamed; Ganguly, Samiran; Stan, Mircea; Ghosh, Avik W. (Charles L. Brown Dept. of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA) |
| S12.3 (2:00PM): Experimentally Validated Pr0.7Ca0.3MnO3 RRAM Verilog-A model based Izhikevich Neuronal Dynamics
Omkar Phadke1, Arpan De2, Jayatika Sakhuja1, Vivek Saraswat1, and Udayan Ganguly1 (1Department of Electrical Engineering, IIT Bombay, Mumbai, India and 2Dept. of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata, India) |
| S12.4 (2:20PM): Equivalent Circuit Macro-Compact Model of the 1T Bipolar SRAM Cell
Semiwise Ltd. Tapas Dutta1, Fikru Adamu-Lema1, Daniel Nagy1, Asen Asenov1, Valerii Nebesnyi2, Jin-Woo Han3, and Yuniarto Widjaja3 (1Semiwise Ltd., Glasgow, Scotland, UK, 2MCPG and 3Zeno Semiconductor Inc., Cupertino, CA, USA) |
| S12.5 (2:40PM): Modeling of Doping Effects in Surface Potential Based Compact Model of Fully Depleted SOI MOSFET
Sébastien Martinie1, Olivier Rozeau1, Plamen Kole2, Patrick Scheer3, Salim El Ghouli3, André Juge3, Harrison Lee4, and Thierry Poiroux1 (1CEA, LETI, Univ. Grenoble Alpes, Grenoble, France, 2Qualcomm, USA, 3STMicroelectronics, France and 4Samsung, South Korea) |
S13: Optoelectronics
Chair:Madhuchhanda Brahma (The University of Texas at Dallas, USA)| S13.1 (1:30PM): Invited: Single Photon Avalanche Diode with Monte Carlo Simulations: PDP, Jitter and Quench Probability
Denis Rideau1, Y. Oussaiti1, J. Grebot1, R. Helleboid1, A. Lopez2, G. Mugny1, E. Bourreau1, D. Golanski1, B. Mamdy1, H. Wehbe Alause1, I. Nicholson2, S. Pellegrini2, C.E. Vlimant2, M. Agnew2, T. Cazimajou3, M. Pala3, J. Saint-Martinand3 and P. Dollfus3 (1STMicroelectronics, France, 2STMicroelectronics, UK and 2Centre de Nanosciences et de Nanotechnologies, Université Paris-Saclay, Palaiseau, France) |
| S13.2 (2:00PM): Potential Engineering to Enhance Transfer Characteristics of Advanced CIS Pixel based on VTG – FDTI scheme
Sungchul Kim1, Jae Ho Kim1, UiHui Kwon1, Kyungho Lee2, and Dae Sin Kim1 (1Computational Science and Engineering Team, Data and Information Technology Center, 2Pixel Development Team, System LSI Division, Device Solution Business, Samsung Electronics Co., Ltd., Republic of Korea |
| S13.3 (2:20PM): 3D Electro-optical Simulations for Improving the Photon Detection Probability of SPAD Implemented in CMOS FDSOI Technology
S. Gao1, D. Issartel1, R. Orobtchouk1, F. Mandorlo1, D. Golanski2, A. Cathelin2, and F. Calmon1 (1Univ Lyon, INSA Lyon, CNRS, INL, France and 2STMicroelectronics, France) |